环境为： ubuntu20.04+vcs2018+UVM_1.1d

1. 下载UVM_1.1d源码

下载链接：uvm-1.1d.tar.gz

tar -zxvf uvm-1.1d.tar.gz

下载后解压到当前目录。

2. 修改环境变量

nano ~/.bashrc

输入：

export UVM_HOME=/opt/synopsys/uvm-1.1d  # 此处为解压后的文件夹路径

3. 修改 Makefile 脚本

在/uvm-1.1d 目录下有example文件夹，里面有Makefile.vcs，打开将里面关于VCS部分修改如下：

 VCS =	vcs -full64 -LDFLAGS -Wl,--no-as-needed -sverilog -timescale=1ns/1ns \
	+acc +vpi \
	+define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR \
	+incdir+$(UVM_HOME)/src $(UVM_HOME)/src/uvm.sv \
	$(UVM_HOME)/src/dpi/uvm_dpi.cc -CFLAGS -DVCS

4. 运行范例

进入到以下目录：

cd /uvm-1.1d/examples/integrated/ubus/examples

运行：

make -f Makefile.vcs

得到以下输出：

----------------------------------------------------------
Name                Type                  Size  Value     
----------------------------------------------------------
ubus_transfer_inst  ubus_transfer         -     @542      
  addr              integral              16    'h785c    
  read_write        ubus_read_write_enum  32    READ      
  size              integral              32    'h1       
  data              da(integral)          1     -         
    [0]             integral              8     'hac      
  wait_state        da(integral)          0     -         
  error_pos         integral              32    'h0       
  transmit_delay    integral              32    'h0       
  master            string                10    masters[1]
  slave             string                9     slaves[1] 
  begin_time        time                  64    3000      
  end_time          time                  64    3040      
----------------------------------------------------------

UVM_INFO ../../../../src/base/uvm_objection.svh(1267) @ 3090: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO ubus_example_scoreboard.sv(113) @ 3090: uvm_test_top.ubus_example_tb0.scoreboard0 [ubus_example_scoreboard] Reporting scoreboard information...
----------------------------------------------------------------
Name                     Type                     Size  Value   
----------------------------------------------------------------
scoreboard0              ubus_example_scoreboard  -     @512    
  item_collected_export  uvm_analysis_imp         -     @520    
    recording_detail     uvm_verbosity            32    UVM_FULL
  disable_scoreboard     integral                 1     'h0     
  num_writes             integral                 32    'd14    
  num_init_reads         integral                 32    'd14    
  num_uninit_reads       integral                 32    'd14    
  recording_detail       uvm_verbosity            32    UVM_FULL
----------------------------------------------------------------

UVM_INFO ../sv/ubus_master_monitor.sv(204) @ 3090: uvm_test_top.ubus_example_tb0.ubus0.masters[0].monitor [uvm_test_top.ubus_example_tb0.ubus0.masters[0].monitor] Covergroup 'cov_trans' coverage: 32.083332
UVM_INFO ../sv/ubus_master_monitor.sv(204) @ 3090: uvm_test_top.ubus_example_tb0.ubus0.masters[1].monitor [uvm_test_top.ubus_example_tb0.ubus0.masters[1].monitor] Covergroup 'cov_trans' coverage: 34.166664
UVM_INFO ../sv/ubus_slave_monitor.sv(242) @ 3090: uvm_test_top.ubus_example_tb0.ubus0.slaves[0].monitor [uvm_test_top.ubus_example_tb0.ubus0.slaves[0].monitor] Covergroup 'cov_trans' coverage: 30.000000
UVM_INFO ../sv/ubus_slave_monitor.sv(242) @ 3090: uvm_test_top.ubus_example_tb0.ubus0.slaves[1].monitor [uvm_test_top.ubus_example_tb0.ubus0.slaves[1].monitor] Covergroup 'cov_trans' coverage: 27.916666
UVM_INFO ../sv/ubus_slave_monitor.sv(242) @ 3090: uvm_test_top.ubus_example_tb0.ubus0.slaves[2].monitor [uvm_test_top.ubus_example_tb0.ubus0.slaves[2].monitor] Covergroup 'cov_trans' coverage: 27.916666
UVM_INFO ../sv/ubus_slave_monitor.sv(242) @ 3090: uvm_test_top.ubus_example_tb0.ubus0.slaves[3].monitor [uvm_test_top.ubus_example_tb0.ubus0.slaves[3].monitor] Covergroup 'cov_trans' coverage: 0.000000
UVM_INFO test_lib.sv(70) @ 3090: uvm_test_top [test_2m_4s] ** UVM TEST PASSED **

--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :  106
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[RNTST]     1
[TEST_DONE]    10
[loop_read_modify_write_seq]     2
[test_2m_4s]     2
[ubus_bus_monitor]    42
[ubus_example_scoreboard]    43
[uvm_test_top.ubus_example_tb0.ubus0.masters[0].monitor]     1
[uvm_test_top.ubus_example_tb0.ubus0.masters[1].monitor]     1
[uvm_test_top.ubus_example_tb0.ubus0.slaves[0].monitor]     1
[uvm_test_top.ubus_example_tb0.ubus0.slaves[1].monitor]     1
[uvm_test_top.ubus_example_tb0.ubus0.slaves[2].monitor]     1
[uvm_test_top.ubus_example_tb0.ubus0.slaves[3].monitor]     1
$finish called from file "../../../../src/base/uvm_root.svh", line 430.
$finish at simulation time                 3090
           V C S   S i m u l a t i o n   R e p o r t 
Time: 3090 ns
CPU Time:      0.210 seconds;       Data structure size:   0.6Mb
Sat Dec 21 19:24:32 2024